Cypress Semiconductor /psoc63 /CPUSS /CM4_NMI_CTL

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Interpret as CM4_NMI_CTL

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0MUX0_SEL

Description

CM4 NMI control

Fields

MUX0_SEL

System interrupt select for CPU NMI. The reset value ensure that the CPU NMI is NOT connected to any system interrupt after DeepSleep reset.

Links

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